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[AKD4345-A]
AKD4345-A
AK4345 Evaluation Board Rev.2
GENERAL DESCRIPTION The AKD4345-A is an evaluation board for the AK4345, 24bit and 96kHz DAC with DIT for portable and home audio systems. The AKD4345-A has the interface with AKM's A/D converter evaluation boards and the interface with digital audio systems via optical connector. Therefore, it is easy to evaluate the AK4345. Ordering guide
AKD4345-A --AK4345 Evaluation Board
FUNCTION * Compatible with 2 types of input data interface - Direct interface with AKM's A/D converter evaluation boards via 10-pin header - On-board AK4112B as DIR, which accepts optical or BNC Inputs * Optical output for internal DIT * BNC connector for an external clock input * BNC connector for DAC output
DGND
VCC
VDD AGND
Digital In OPT BNC MCLK
74LVC541 AK4112B (DIR)
AK4345
Digital Out OPT Analog Out LOUT
Clock Divider Generator 10pin Header DSP Data
Figure 1. AKD4345-A Block Diagram
ROUT
* Circuit diagram and PCB layout are attached at the end of this manual.
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[AKD4345-A]
Operation sequence
1) Set up the power supply lines. [VDD] (Red) = 2.7 3.6V (typ. 3.3V, for AK4345) [VCC] (Red) = 2.7 3.6V (typ. 3.3V, for AK4112B, for 74LVC541 and for logic) [AGND] (Black) = 0V [DGND] (Black) = 0V Each supply line should be distributed from the power supply unit. 2) Set-up the evaluation modes, jumper pins and DIP switches (See the followings.) 3) Power on. When AK4112B is used, The AK4112B and AK4345 should be reset once by bringing SW2 and SW1 "L" upon power-up. When AK4112B is not used, keep SW2 to "L", and the AK4345 should be reset once by bringing SW1 "L" upon power-up.
Evaluation mode
1) D/A part evaluation using optical or S/PDIF input Use PORT1 (RX1: OPT) or J2 (RX1: BNC). The AK4112B (DIR) generates MCLK, BICK, LRCK and SDTI1 from the received data through Optical connector (TORX141) or BNC connector. This evaluation mode should be used for the evaluation using CD test disk. Nothing should be connected to PORT3 (DSP). The selection of OPT and BNC should be done by JP14 (RX1)
JP4 MCLK JP5 BICK JP6 SDTI1 JP7 LRCK JP12 EXT
DIR
EXT
DIR
EXT
DIR
EXT
2) D/A part evaluation using 10-pin connector on the AKM's A/D evaluation board Use PORT3 (DSP). It is able to evaluate the AK4345, connecting the 10-pin connector on the AKM's A/D evaluation board and PORT3 (DSP) via 10-line flat cable. MCLK, BICK, LRCK and SDTI1 are sent from the A/D converter evaluation board to the AKD4345 through PORT3 (DSP) via 10-line flat cable.
JP4 MCLK JP5 BICK JP6 SDTI1 JP7 LRCK JP12 EXT
DIR
EXT
DIR
EXT
DIR
EXT
3) D/A part evaluation using PORT3 (DSP), and supplying all interface signals from external equipments In case of using PORT3 (DSP), and supplying signals (MCLK, BICK, LRCK, SDTI1) that is needed for the AK4345 from external equipments, set up as following.
JP4 MCLK JP5 BICK JP6 SDTI1 JP7 LRCK JP12 EXT
DIR
EXT
DIR
EXT
DIR
EXT
In case of using PORT3 (DSP), and supplying SDTI2 from external equipments, setting of SDTI2 should be done by JP8 (SDTI2). -22007/07
[AKD4345-A]
Other Jumper pins set up
(1) JP15 (VDD): VDD and VCC OPEN: Separated SHORT: Common. (The connector "VCC" can be open.) By opening the connector "VCC", shorting JP15 (VDD) and supplying 3.3V to the connector "VDD", the connector "VDD" can supply 3.3V to all circuits (2) JP16 (GND): Analog ground and Digital ground OPEN: Separated SHORT: Common. (The connector "DGND" can be open.) (3) JP10 (BCFS): Select the BICK of the AK4345 x1: BICK=128fs in case of MCLK=256fs/384fs/512fs/768fs. BICK=64fs in case of MCLK=192fs. x2: BICK=64fs in case of MCLK=128fs/256fs/384fs/512fs/768fs. SDTI2: Select the SDTI2 (6) JP8 (SDTI2): Select the input of SDTI2 pin PORT3: Input the signal from PORT3 GND: Input the "0" Data (When JP2 (CDTO / SDTI2): setting is CDTO, Set to GND)
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Example for External Clock setting
Refer to the following setting when MCLK, BICK and LRCK are supplied to the AK4345 from J1 (EXT). Mode fs 8kHz Half 24kHz MCLK JP11 (DIV) JP9 (CLK) 512fs = 4.096MHz x2 x2 768fs = 6.144MHz x3 x2 1024fs = 8.192MHz x2 x2 1536fs = 12.288MHz x3 x2 512fs = 12.288MHz x2 x2 768fs = 18.432MHz x3 x2 1024fs = 24.576MHz x2 x2 1536fs = 36.864MHz x3 x2 256fs = 2.048MHz x1 x2 384fs = 3.072MHz OPEN x3 512fs = 4.096MHz x2 x2 768fs = 6.144MHz x3 x2 256fs = 8.192MHz x1 x2 384fs = 12.288MHz OPEN x3 512fs = 16.384MHz x2 x2 768fs = 24.576MHz x3 x2 256fs = 11.2896MHz x1 x2 384fs = 16.9344MHz OPEN x3 512fs = 22.5792MHz x2 x2 768fs = 33.8688MHz x3 x2 256fs = 12.288MHz x1 x2 384fs = 18.432MHz OPEN x3 512fs = 24.576MHz x2 x2 768fs = 36.864MHz x3 x2 128fs = 6.144MHz OPEN x1 192fs = 9.216MHz OPEN x3 256fs = 12.288MHz x1 x2 384fs = 18.432MHz OPEN x3 128fs = 12.288MHz OPEN x1 192fs = 18.432MHz OPEN x3 256fs = 24.576MHz x1 x2 384fs = 36.864MHz OPEN x3 Table 1. Clock Setting JP13 (LRFS) x1 x1 x2 x2 x1 x1 x2 x2 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x3 x1 x1 x1 x3 x1 x1
8kHz
32kHz Normal 44.1kHz
Default
48kHz
48kHz Double 96kHz
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[AKD4345-A]
DIP Switch set up
[SW3]: Setting the audio data format of the AK4112B (ON="H", OFF="L") Mode 0 3 4 5 SW3-3 SW3-2 SW3-1 SDTI Format DIF2 DIF1 DIF0 L L L 16bit, LSB justified L H H 24bit, LSB justified H L L 24bit, MSB justified H L H 24bit, I2S Compatible Table 2. SW3: Audio Data Format of AK4112B
Default
Note. The AK4112B does not support 16bit, I2S Compatible.
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[AKD4345-A]
The function of the toggle SW
[SW1] (AK4345-PDN): Resets the AK4345. Keep "H" during normal operation. The AK4345 should be reset once by bringing SW1 "L" upon power-up. [SW2] (AK4112B-PDN): Resets the AK4112B. Keep "H" during normal operation. The AK4112B should be reset once by bringing SW2 "L" upon power-up.
Analog Output Circuit
The DAC of AK4345 outputs analog audio signals through J3 and J4. C13 22u
+ AK4345-LOUT R9 10k J3 BNC-R-PC
1 2 LOUT 3 4 5
R7 220
C100 1n
C17 22u + AK4345-ROUT R13 10k
R12 220
J4 BNC-R-PC
1 2 ROUT 3 4 5
C101 1n
Figure 2. LOUT/ROUT Output circuit
* AKEMD assumes no responsibility for the trouble when using the above circuit examples.
Serial control
The AKD4345-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (uP-I/F) to PC by 10-line flat cable packed with the AKD4345-A. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT4 as shown Figure 3.
PORT4 uP I/F 2
GND
GND
GND
GND
GND
10
Red
Figure 3. PORT4 pin layout
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CDTO
1
CCLK CSN
CDTI
NC
9
2007/07
[AKD4345-A]
Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4345-A according to the Operating Sequence located on page 2. 2. Connect IBM-AT compatible PC with AKD4345-A by 10-line type flat cable (packed with AKD4345-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4345-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4345-A.exe" to set up the control program. 5. Please evaluate according to the following.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button.
Explanation of each buttons
1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4345. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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[AKD4345-A]
Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4345, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK4345, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate ATT
Address Box: Start Data Box: End Data Box: Interval Box: Step Box: Input registers address in 2 figures of hexadecimal. Input starts data in 2 figures of hexadecimal. Input end data in 2 figures of hexadecimal. Data is written to AK4345 by this interval. Data changes by this step.
Mode Select Box: *If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 *If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4345, click [OK] button. If not, click [Cancel] button.
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[AKD4345-A]
4. [Save] and [Open] 4-1. [Save]
Save the current register setting data. The extension of file name is "akr".
(Operation flow)
(1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr". 4-2. [Open] The register setting data saved by [Save] is written to AK4345. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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[AKD4345-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is "aks".
Figure 4. Window of [F3]
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[AKD4345-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure opens.
Figure 5. [F4] window
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[AKD4345-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure.
Figure 6. [F4] window(2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The sequence file names can assign be saved. The file name is *.ak4. [OPEN]: The sequence file names assign that are saved in *.ak4 are loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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[AKD4345-A]
7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure opens.
Figure 7. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
(2) Click [WRITE] button, then the register setting is executed.
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
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[AKD4345-A]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * BICK * fs * BW * Bit * Power Supply * Interface * Temperature [Measurement Results] Parameter DAC Analog Output Characteristics S/(N+D) (fs=44.1kHz, fin=1KHz, 0dBFS) (fs=96kHz, fin=1KHz, 0dBFS) D-Range (fs=44.1kHz, fin=1KHz, -60dBFS, A-weighted) (fs=96kHz, fin=1KHz, -60dBFS, A-weighted) S/N (fs=44.1kHz, no-input, A-weighted) (fs=96kHz, no-input, A-weighted) Interchannel Isolation (fin=1KHz, 0dBFS/no-input) dB dB dB Results Lch / Rch Unit
: Audio Precision, System Two Cascade : 512fs (fs=44.1KHz) /256fs (fs=96KHz) : 64fs : 44.1kHz / 96kHz : 20Hz~20KHz (fs=44.1kHz) / 20Hz~40KHz (fs=96kHz) : 24bit : VDD = 3.3V : PSIA : Room
dB dB dB dB
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[AKD4345-A]
AKM
-70 -72 -74 -76 -78 -80 -82 d B r A -88 -90 -92 -94 -96 -98 -100 -140 -84 -86
THD+N vs. Input Level fs=44.1kHz, fin=1kHz
06/18/07 09:30:43
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
AKM
-70 -72 -74 -76 -78 -80 -82 d B r A -88 -90 -92 -94 -96 -98 -100 20 -84 -86
THD+N vs. Input Freqency fs=44.1kHz, fin=0dBFs
06/18/07 09:28:48
50
100
200
500 Hz
1k
2k
5k
10k
20k
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[AKD4345-A]
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
Linearity fs=44.1kHz, fin=1kHz
06/18/07 09:35:13
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
AKM
+1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2k 4k
Freqency Response fs=44.1kHz, fin=0dBFs
06/18/07 09:49:36
6k
8k
10k Hz
12k
14k
16k
18k
20k
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[AKD4345-A]
AKM
-70
Crosstalk fs=44.1kHz
06/18/07 09:56:53
-76
-82
-88
-94 d B
-100
-106
-112
-118
-124
-130 10
20
50
100
200
500 Hz
1k
2k
5k
10k
20k
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50
FFT fs=44.1kHz, fin=0dBFs,1kHz
06/18/07 10:07:31
100
200
500 Hz
1k
2k
5k
10k
20k
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[AKD4345-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50
FFT fs=44.1kHz, fin=-60dBFs,1kHz
06/18/07 10:08:53
100
200
500 Hz
1k
2k
5k
10k
20k
-
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100
FFT Noise floor fs=44.1kHz
06/18/07 10:09:30
200
500 Hz
1k
2k
5k
10k
20k
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[AKD4345-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100
FFT Out-of-band Noise fs=44.1kHz
06/18/07 10:32:35
200
500
1k Hz
2k
5k
10k
20k
50k
100k
-70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 d B r A -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0
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[AKD4345-A]
-70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 d B r A -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 10 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
Linearity fs=96kHz
06/18/07 10:46:53
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
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2007/07
[AKD4345-A]
AKM
+1 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 d B r A +0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2.5k 5k 7.5k 10k
Frequency response fs=96kHz
06/18/07 10:49:42
12.5k
15k
17.5k
20k Hz
22.5k
25k
27.5k
30k
32.5k
35k
37.5k
40k
AKM
-70 -75 -80 -85 -90 -95 d B -100 -105 -110 -115 -120 -125 -130 10
Crosstalk fs=96kHz
06/18/07 10:52:01
20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
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[AKD4345-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50
FFT fs=96kHz, fin=0dBFs,1kHz
06/18/07 10:24:00
100
200
500 Hz
1k
2k
5k
10k
20k
40k
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50
FFT fs=96kHz, fin=-60dBFs,1kHz
06/18/07 10:28:58
100
200
500 Hz
1k
2k
5k
10k
20k
40k
-
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2007/07
[AKD4345-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100
FFT Noise floor fs=96kHz
06/18/07 10:29:37
200
500 Hz
1k
2k
5k
10k
20k
40k
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 10 20 50 100
FFT Out-of-band Noise fs=96kHz
06/18/07 10:30:24
200
500
1k Hz
2k
5k
10k
20k
50k
100k
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[AKD4345-A]
Revision History Date (yy/mm/dd) 07/03/15 07/04/17 Manual Revision KM087800 KM087801 Board Revision 0 1 Reason First Edition Circuit Change Change Circuit Change Add Contents
07/07/02
KM087802
2
Change U1 (AK4345): 28pin SOP 16pin TSSOP Remove jumper pins: JP1 (TX), JP3 (TEST1). Add resistance: R100 (300) to TX. TEST1 is open. P3. Remove description: (7) JP1 (TX), (8) JP3 (TEST1). Capacitor between VCOM and VSS: C3: Change: 10uF 4.7uF Add capacitor C100: 1nF between J3 (LOUT) and GND. Add capacitor C101: 1nF between J4 (ROUT) and GND. Add measurement results
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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2007/07
A
B
C
D
E
E
E
CN1
U1 R100
CN2
AK4345-MCLK
D
1
1
MCLK
TX
16
16
AK4345-TX
D
AK4345-BICK
2
2
BICK
CDTO/SDTI2
15
CDTO JP2(3x1) CDTO/SDTI2 SDTI2
300
15
AK4345-CDTO
AK4345-SDTI1
3
3
SDTI1
VDD
14
14
AK4345-SDTI2
C1 0.1u AK4345-LRCK
4 4 LRCK VSS 13
+
C2 10u
13
VDD
AK4345-PDN
C
5
5
PDN
VCOM
12
AK4345-CSN
6
6
CSN
LOUT
11
AK4345-CCLK
7
7
CCLK
ROUT
10
AK4345-CDTI
8
8
CDTI
TEST1
9
AK4345
B B
A
A
B
C
+
12 11
C3 4.7u
AK4345-LOUT
C
10
AK4345-ROUT
9
A
Title
Size
Date:
D
AKD4345-A A4 AK4345 Tuesday, June 12, 2007
Document Number Sheet
E
Rev
2
of
1
6
A
B
C
D
E
U2
E
VCC C4 10u C6 10u VCC + C5 0.1u
1
DVDD
CM0/CDTO
28
E
2
DVSS
CM1/CDTI
27
VCC
C8
D
X1 HC-49/U 11.2896MHz
6 XTO MCKO2 23
C9
AK4112B-PDN R1
C
VCC C10 10u + C11 0.1u
AK4112B-RX1
AK4112B-DIF0
B
AK4112B-DIF1
AK4112B-DIF2
A
A
+ + 5p 5p 18k
B
C7 0.1u
3 TVDD OCKS1/CCLK 26
VCC
4
V/TX
OCKS0/CSN
25
5
XTI
MCKO1
24
AK4112B-MCKO1
D
7
PDN
DAUX
22
8
R
BICK
21
AK4112B-BICK
9
AVDD
SDTO
20
AK4112B-SDTO
C
10
AVSS
LRCK
19
AK4112B-LRCK
11
RX1
ERF
18
AK4112B-ERF
12
RX2/DIF0
FS96
17
13
RX3/DIF1
P/S
16
VCC
B
14
RX4/DIF2
AUTO
15
AK4112B
A
Title Size
Document Number
A4
Date:
C D
AKD4345-A AK4112B
Sheet
E
Rev
2
2
of
Thursday, May 31, 2007
6
A
B
C
D
E
E
E
VCC U3
1
G1
VCC
20
C12 0.1u
19 G2 GND 10
D
EXT-MCLK AK4112B-MCKO1 EXT-BICK AK4112B-BICK AK4112B-SDTO EXT-LRCK AK4112B-LRCK
EXT DIR EXT DIR
EXT DIR
PORT3-MCLK JP4(3x1) MCLK PORT3-BICK JP5(3x1) BICK PORT3-SDTI1 JP6(2x1) SDTI1 PORT3-LRCK JP7 (3x1) LRCK 74LVC541A-PDN
R2
2 A1 Y1 18
51 AK4345-MCLK
D
R3
3 A2 Y2 17
51 AK4345-BICK
R4
4 A3 Y3 16
51 AK4345-SDTI1
R5
5 A4 Y4 15
51 AK4345-LRCK
C
C
6
A5
Y5
14
AK4345-PDN
PORT3-SDTI2
PORT3 GND
JP8 (3x1) SDTI2
7
A6
Y6
13
AK4345-SDTI2
8
A7
Y7
12
9
A8
Y8
11
B
B
74LVC541A
A
A
Title Size Document Number
A4
Date:
A B C D
AKD4345-A 74LVC541A
Sheet
E
Rev
2
of
Thursday, May 31, 2007
3
6
A
B
C
D
E
EXT-MCLK
E
VCC U4A 74AC74
Q 5
E
14 10
GND CL
VCC PR
EXT
2 3 4 5
D
D
Q
1
11
Q
6
CLK
11
CLK RST
VCC
J1 BNC-R-PC
12
9
x1 1 x2 3 x3 5 DIV
2 4 6
3
16
VCC
D
VCC PR
U4B 74AC74
JP11 (3x2)
14 4
JP9 (3x2) x1 1 x2 3 x3 5
2 4 6 10
VCC x1 x2 x4 x8
1 2 3 4
JP10 (4x2)
5 6 7 8
2
CLK
GND CL
CLK
7 13
R6 51 EXT JP12 (2x1)
Q
8
VCC U6 74AC163
3 4 5 6 7 10 2 9 1 A B C D
16
14
VCC
QA QB QC QD RCO 14 13 12 11 15 1
U5 74HC4040
2
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
GND
9 7 6 5 3 2 4 13 12 14 15 1
EXT-BICK
BCFS
7 1
JP13 (3x2) x3 1 x1 3 x2 5
2 4 6
D
EXT-LRCK
LRFS
VCC
U7A 74HC14
C
ENP ENT CLK LOAD CLR
3 GND
7
4
U7B 74HC14
C
8
5
6
U7C 74HC14
9 8
U7D 74HC14
11 10
U7E 74HC14
B B
13
12
U7F 74HC14
A
8
A
Title Size Document Number
AKD4345-A
External Master Clock Divider
Sheet
E
Rev
A4
Date:
A B C D
2
6
Thursday, May 31, 2007
4
of
A
B
C
D
E
VCC
2
VCC
1
L1 47u PORT1 TORX141 D1 HSU119 R8 10k U8A
1 2 3
C13 22u + AK4345-LOUT
R7 220
1
J3 BNC-R-PC
2 LOUT 3 4 5
K
E
RX1(OPT) U8B
4
VCC GND OUT
3 2 1
C14 0.1u R10 470 OPT JP14 (3x1) AK4112B-RX1 RX1
A
R9 10k
C100 1n
E
74LVC541A-PDN
L
3
H
1
74HC14 C15 0.1u
74HC14 J2 BNC-R-PC
1
SW1 ATE1D-2M3 AK4345-PDN
2
RX1(BNC)
2 3 4 5
C16 R11 75 0.1u
BNC
C17 22u + VCC
D
R12 220
1
J4 BNC-R-PC
2 ROUT 3 4 5
AK4345-ROUT PORT2 TOTX141 R14 10k U8C
5 6 9
A
D2 HSU119
TX(OPT) U8D
8
IN VCC GND
K
3 2 1
AK4345-TX VCC C18 0.1u
R13 10k
C101 1n
D
AK4112B-PDN
L
3
H
1
74HC14 C19 0.1u
74HC14
SW2 ATE1D-2M3 AK4112B-PDN
2
C
C
SW3 DSS103 DIF0 DIF1 DIF2
1 2 3 4 5 6
VCC
PORT3-MCLK PORT3-BICK PORT3-LRCK PORT3-SDTI1 PORT3-SDTI2 PORT3 A1-10PA-2.54DSA 1 10 MCLK 2 9 BICK 3 8 LRCK 4 7 SDTI1 SDTI2 5 6 DSP
AK4112B-MODE R15 R16 R17 47K 47K 47K AK4112B-DIF0 AK4112B-DIF1 AK4112B-DIF2 U9A 74HCT04 AK4112B-ERF
B
R18 1k
LED1 SML-210VT
K A
1
2
VCC
AK4112B-ERF
B
U9B 74HCT04
3 4
U8E
11 10
VCC U10 74HCT157
1Y 2Y 3Y 4Y GND 4 7 9 12
U9C 74HCT04
14 5 6 13 7
74HC14 VCC U8F
12
U9D 74HCT04
9 8
R22 R25
10k 10k
R23 R26
470 470
74HC14
U9E 74HCT04
11 10
1A 1B 2A 2B 3A 3B 4A 4B A/B G
VCC
R19
10k
R20
470
16
VCC
2 3 5 6 11 10 14 13 1 15
R21 R24 R27 R28 R29 100K
100 100 100 100
AK4345-CSN AK4345-CCLK AK4345-CDTI AK4345-CDTO
U9F 74HCT04
12
14
2
1
13 7
8
A
VCC
PORT4 A1-10PA-2.54DSA 10 9 CSN 8 7 CCLK 6 5 CDTI 4 3 CDTO uP-I/F R30 (short)
A
Title Size
AKD4345-A
Document Number Rev
A3
Date:
A B C D
Input Output for Digital Analog Sheet of
Tuesday, June 12, 2007 5 6
E
2
A
B
C
D
E
E
VDD T_45(RED)
VCC T_45(RED)
AGND DGND T_45(BLACK)T_45(BLACK)
E
1
1
1
VDDi
VCCi
AGND
DGND
VDDi
1
D
VCCi
1
D
L2 (short)
2
L3 (short) JP15 (2x1) VDD C21 47u + R31 (short) C22 0.1u R32 C23 0.1u C24 0.1u C25 0.1u C26 0.1u C27 0.1u C28 0.1u For 74HC14 x 1, 74HCT04 x 1, 74AC74 x 1, 74HC4040 x 1, 74AC163 x 1, 74HC14 x 1 VCC
2
C20 47u +
C
1
VDD (short)
C
JP16 AGND (2x1) DGND GND
B
B
A
A
Title Size Document Number
A4
Date:
A B C D
AKD4345-A Power Supply
Sheet
E
Rev
2
of
Thursday, May 31, 2007
6
6

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